EV4101【PDF 6/68 页】32-bit Microprocessor that Executes MIPS

TinyRISC

EV4101 Microprocessor Reference Device Technical Summary

2 Features

Includes the TR4101 microprocessor core, XC module, and BBCC,

MDU, timer, DBX module, and SerialICE port building blocks

MIPS I, MIPS II, and MIPS16 instruction set implementation

Low power management features

16 Kbyte two-way set-associative instruction cache (I-cache)

8 Kbyte direct-mapped data cache (D-cache)

Four-deep write buffer

Hardware and application software debug support with SerialICE

3.3-volt, 0.29-micron, cell-based G10

-p CMOS process technology

Cache controller offers advanced instruction and data streaming

Load scheduling support

Two 16-bit programmable timers

Basic PCI-like 32-bit memory interface

Full- or half-speed bus clock options

Dual bus arbitration configurations for either host or nonhost

operation

66 MHz at wccom, when executing MIPS I, MIPS II, and MIPS16

3.3-volt operation, 5-volt tolerant inputs

66 MIPS peak performance and 53 MIPS sustained at 66 MHz

3 Block Diagram

This section describes the internal blocks in the EV4101 Reference

Device, shown in Figure 1.

The TR4101 microprocessor core is the main component of the EV4101

Reference Device. The EV4101 executes all MIPS II 32-bit based

instructions except for the multiprocessor support instructions. In

addition, it executes all but the double word MIPS16 instructions. The

microprocessor is implemented with an efficient three-stage pipeline that

is extended to four stages for Load Word (LW) and Store Word (SW) type

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